Figure 3 from The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters | Semantic Scholar (2024)

This paper compares a high speed second-order sigma-delta (/spl Sigma//spl Delta/ modulator) to several alternative modulator architectures in the context of large bandwidth signal acquisition and achieves a large bandwidth and a linear integration.

This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampled ratio is constrained by technology limitations.

An analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated and this architecture shows promise for obtaining high speed and resolution conversion.

Over Sampling concept is used to address the problem of power Dissipation, noise in ADCs and investigating the possibilities of utilizing alternative methods to reduce the noise and power dissipation in ADC architectures.

A novel formal method for scaling oversampled and analogue-to-digital converters based on well-founded system theory concepts is introduced and the application of the scaling method to a multi-stage ΣΔ analogue- to-digital structure is illustrated.

A 12-b sigma-delta ( Sigma - Delta ) analog-to-digital (A/D) converter has been designed and fabricated using a 2- mu m CMOS double-poly process and preliminary test results are reported.

An analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated and this architecture shows promise for obtaining high speed and resolution conversion.

A double-sampling technique is introduced for extended-counting analog-to-digital conversion, based on a variant of the fully floating bilinear integrator, which can be realized with only one operational amplifier.

This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply and introduces a cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes.

An analytical comparison of noise performance in four alternative sigma–delta circuit configurations, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode shows superiority of switched-capacitor circuits over the alternatives.

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This approach requires no internal D/A converter, nor does it produce a coarser quantization with larger inputs, and can display a net resolution exceeding the performance of the internal analog components, and since the bulk of the circuitry is digital, it benefits from continued technology scalmg.

A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming and was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.

A practical method for overcoming a thresholding action that distorts low-amplitude input signals and use of appropriate weights in the accumulation has important advantages for providing finer resoution, less spectral distortion, and white quantization noise.

An alternative set of parameters for characterizing the linear, nonlinear, and statistical properties of analog-to-digital (A/D) converters is suggested, and an algorithm, referred to as the sinusoidal minimum error method is proposed to estimate the values of these parameters.

A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC, achieving integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion.

An approach to the implementation of multi-channel telecommunication interfaces using oversampled techniques using Fully-differential techniques are applied to the analog front end to reduce crosstallc and improve power supply rejection.

A description is given of a high-performance fifth-order low-pass switched-capacitor filter operating form a single 5-V supply that uses a fully differential topology combined with input-to-output class AB amplifier design, dynamic biasing, and switched-Capacitor common-mode feedback to meet the PCM channel filter requirements.

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