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Topics

Sigma Delta (opens in a new tab)Modulator (opens in a new tab)Oversampling (opens in a new tab)

747 Citations

VLSI implementation of a high speed second order sigma-delta modulator with high-performance integrators
    E. HosseinzadehJ. BelzileC. Thibeault

    Engineering, Computer Science

    Conference Proceedings. IEEE Canadian Conference…

  • 1998

This paper compares a high speed second-order sigma-delta (/spl Sigma//spl Delta/ modulator) to several alternative modulator architectures in the context of large bandwidth signal acquisition and achieves a large bandwidth and a linear integration.

  • 1
A 2.5-V sigma-delta modulator for broadband communications applications
    K. VleugelsS. RabiiB. Wooley

    Engineering, Computer Science

    IEEE J. Solid State Circuits

  • 2001

This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampled ratio is constrained by technology limitations.

  • 160
Design Issues of the Parallel Delta-Sigma A / DConverterEric T
    E. KingA. EshraghiI. GaltonT. Fiez

    Computer Science, Engineering

  • 2007

An analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated and this architecture shows promise for obtaining high speed and resolution conversion.

  • Highly Influenced
Design and VLSI Implementation of Second Order Sigma-Delta Modulation ADC for I-UWB Receiver
    K.Lokesh KrishnaT.RamashriD.Srihari

    Computer Science, Engineering

  • 2013

Over Sampling concept is used to address the problem of power Dissipation, noise in ADCs and investigating the possibilities of utilizing alternative methods to reduce the noise and power dissipation in ADC architectures.

Scaling of analogue-to-digital sigma-delta modulators
    A. Salama

    Engineering

  • 1996

A novel formal method for scaling oversampled and analogue-to-digital converters based on well-founded system theory concepts is introduced and the application of the scaling method to a multi-stage ΣΔ analogue- to-digital structure is illustrated.

Design, fabrication, and testing of a 12-bit sigma-delta analog to digital converter
    D. MoonanG. Fischer

    Engineering

    [1992] Proceedings of the 35th Midwest Symposium…

  • 1992

A 12-b sigma-delta ( Sigma - Delta ) analog-to-digital (A/D) converter has been designed and fabricated using a 2- mu m CMOS double-poly process and preliminary test results are reported.

A Nyquist-rate delta-sigma A/D converter
    E. KingA. EshraghiI. GaltonT. Fiez

    Engineering

    IEEE J. Solid State Circuits

  • 1998

An analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated and this architecture shows promise for obtaining high speed and resolution conversion.

  • 64
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A double-sampling extended-counting ADC
    J. D. MaeyerP. RomboutsL. Weyten

    Computer Science, Engineering

    IEEE Journal of Solid-State Circuits

  • 2004

A double-sampling technique is introduced for extended-counting analog-to-digital conversion, based on a variant of the fully floating bilinear integrator, which can be realized with only one operational amplifier.

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A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS
    S. RabiiB. Wooley

    Computer Science, Engineering

    IEEE J. Solid State Circuits

  • 1997

This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply and introduces a cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes.

  • 231
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Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology
    Noam DolevA. KornfeldA. Kolodny

    Engineering

    J. Circuits Syst. Comput.

  • 2005

An analytical comparison of noise performance in four alternative sigma–delta circuit configurations, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode shows superiority of switched-capacitor circuits over the alternatives.

  • 4
  • PDF

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31 References

MOS ADC-filter combination that does not require precision analog components
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    Engineering, Physics

    1985 IEEE International Solid-State Circuits…

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This approach requires no internal D/A converter, nor does it produce a coarser quantization with larger inputs, and can display a net resolution exceeding the performance of the internal analog components, and since the bulk of the circuitry is digital, it benefits from continued technology scalmg.

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VLSI- A to D and D to A converters with multi-stage noise shaping modulators
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    ICASSP '86. IEEE International Conference on…

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High resolution oversampling analog-to-digital and digital-to-analog converters are proposed. These converters utilize novel multi-stage noise shaping modulation techniques which can be implemented

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A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate
    R. KochB. HeiseF. EckbauerE. EngelhardtJ. FisherF. Parzefall

    Engineering

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A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming and was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.

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Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator
    J. C. CandyY. ChingD. Alexander

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    IEEE Trans. Commun.

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A practical method for overcoming a thresholding action that distorts low-amplitude input signals and use of appropriate weights in the accumulation has important advantages for providing finer resoution, less spectral distortion, and white quantization noise.

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Simulating and testing oversampled analog-to-digital converters
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An alternative set of parameters for characterizing the linear, nonlinear, and statistical properties of analog-to-digital (A/D) converters is suggested, and an algorithm, referred to as the sinusoidal minimum error method is proposed to estimate the values of these parameters.

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A CMOS 8-Bit High-Speed A/D Converter IC
    A. YukawaT. FujitaK. Hareyama

    Computer Science, Engineering

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A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC, achieving integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion.

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A CMOS pulse density modulator for high-resolution A/D converters
    H. FiedlerB. Hoefflinger

    Engineering, Physics

    IEEE Journal of Solid-State Circuits

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A high-performance pulse density modulator (PDM) has been fabricated using a 3.5-/spl mu/m CMOS silicon gate technology. The PDM comprises all the analog circuitry needed for an interpolative A/D

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A Four-channel CMOS Oversampled PCM Voiceband Coder
    B. LeungR. NeffP. GrayR. Brodersen

    Engineering, Computer Science

    1988 IEEE International Solid-State Circuits…

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An approach to the implementation of multi-channel telecommunication interfaces using oversampled techniques using Fully-differential techniques are applied to the analog front end to reduce crosstallc and improve power supply rejection.

  • 8
A high-performance micropower switched-capacitor filter
    R. CastelloP. Gray

    Engineering, Physics

    IEEE Journal of Solid-State Circuits

  • 1985

A description is given of a high-performance fifth-order low-pass switched-capacitor filter operating form a single 5-V supply that uses a fully differential topology combined with input-to-output class AB amplifier design, dynamic biasing, and switched-Capacitor common-mode feedback to meet the PCM channel filter requirements.

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An analysis of nonlinear behavior in delta-sigma modulators
    S. ArdalanJ. Paulos

    Engineering, Computer Science

  • 1987

This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7],

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